Asynchronous Transfer Mode (ATM) is being developed as a high-speed networking technique for a public network capable of supporting many classes of traffic, and has emerged as a leading technique for high-speed packet switching. ATM is a high-speed, packet-switching technique using short fixed-length packets called cells. Fixed-length cells simplify the design of an ATM switch at the high switching speeds involved. Thus, ATM presents a single integrated switching mechanism capable of supporting a wide range of traffic types such as voice, video, image, and various classes of data traffic. ATM has been selected as the multiplexing and switching technique for use in the public Broadband Integrated Digital Network (BISDN) and is receiving much standardization activity. The switching architecture is the most significant component of an ATM switch's hardware design. It affects the cost, performance, capacity, growth capability, and complexity of the switch design. Accordingly, there have been numerous architectures for ATM switching systems proposed in the literature. However, selecting an architecture involves tradeoffs between ease of implementation and delay-throughput performance. A unique taxonomy of ATM switching architectures is difficult to find, because of the classification of ATM switches. In this thesis, to meet a good tradeoff, we propose some new candidates of ATM switching architecture and propose to use a neural network as the control part in a class of switches. In the following, we simply give a classification of the switching architecture, then in the following sections we will give a summary of the publications involved in this thesis.