This thesis consists of two subjects in a high performance packet switch: the first subject is a conventional solution for design, implementation and performance analysis of an ATM modular switch, and the second subject is a neural network application in a high performance packet switch.

The first subject covers the following topics:

The design of a modular ATM switch is considered. Two modular switch architectures have been proposed. The goal of achieving the modular switches is to relax the limitation of the VLSI implementation, to simplify the interstage wiring and synchronization, and furthermore to reduce the complexity of the overall switch. One switch architecture constructs a pure output queue by providing a multipath in each output port and replicated switching module planes. Another constructs a two-stage delta network with an output queue in each stage. Cell loss in the switches has been analyzed and simulated. According to the statistical traffic character, these switches can achieve very high performance by providing a reasonable number of interconnection lines.

Nonuniform traffic effect on the switch has been investigated. A simulation study of the uniform random traffic and bursty traffic has been carried out in the proposed switches.

Since services require different quality of service, an ATM switch must be capable of handling the requirements of different services. A two-class priority scheme in the Knockout Switch and Generalized Knockout Switch has been studied. Introducing the priorities to the two classes of cells has proved to be one way to maintain quality of services and reduce switching hardware complexity. A very important result has been given that using the priority scheme in the Generalized Knockout Switch is more efficient than in the Knockout Switch to reduce the interconnect complexity of the switch.

The second subject covers the following topics:

The rearrangeable Clos' packet switch has especially attractive advantage in a nonblocking interconnection with less hardware than a nonblocking network can be realized. In addition, the output queuing rearrangeable Clos' switch proposed in this thesis has the best delay/throughput performance. In rearrangeable nonblocking multistage switching networks, a path establishment algorithm is normally required. The problem in a traditional routing method is that the path establishment time depends on the switch size and increases as the switch size increases. In the proposed method of neural network path assignment, the path establishment time no longer depends on the switch size, and the neural network can achieve a throughput which is very close to maximal throughput. In the thesis the equations of the neural network for the routing problem have been developed, while simulations of the neural networks have been carried out in computers.